Ideally, a voltage or current reference circuit provides a stable voltage or current that is independent of power supply and temperature. Many applications in analog circuits require such a stable current or voltage. For example, a small bias current reference is typically required for operation of analog circuits such as comparators and operational amplifiers.
An example of a circuit used to generate such a reference current or voltage is a threshold voltage Vt referenced source also known as a bootstrap reference. In such a reference circuit, the voltage across an active device creates a current that then controls the original current through the device to produce a current or voltage that is independent of the power supply voltage VDD.
An example of a Vt or bootstrap reference using all MOS devices (e.g. all CMOS devices) is the reference circuit 100 illustrated in FIG. 1 which represents a circuit including a reference circuit 120 and a start-up circuit 110. (See, for example, Allen & Holberg, CMOS Analog Circuit Design, p. 240–251, Holt, Rinehart & Winston, New York 1987, which is hereby incorporated by reference). The reference circuit 120 comprises a current mirror 134 including p-channel field effect transistors (FETs) M3 and M4, n-channel FETs M1 and M2, a reference regulator 136 implemented in this example as an n-channel FET M1 and a reference output regulator 138 implemented in this example as a resistance R. The sources of p-channel transistors M3 and M4 are connected to positive voltage supply VDD. The drain of transistor M3 is connected to the gate of n-channel transistor M2 and also to the drain of n-channel transistor M1. The drain of p-channel transistor M4 is connected to the drain of n-channel transistor M2. The gates of transistors M3 and M4 are connected together. The drain of transistor M4 is also connected to the gates of transistors M3 and M4 so that the output voltage VXP is supplied to the gates. N-channel transistor M1 has its drain also connected to the gate of n-channel transistor M2, and its source connected to a ground VSS. The source of transistor M2 is connected to the gate of transistor M1 and to one side of the resistance R. Another side of resistance R is connected to ground VSS.
The p-channel transistors and the n-channel transistors form a feedback circuit which causes the current in n-channel transistor M1 to be the same current supplied to resistance R. In other words, the voltage VGS1 appears as the voltage V across R. In post-start-up operation, the p-channel transistors M3 and M4 are assumed to be matched devices forming a current mirror unit producing equal currents, I1 and I2, to flow from the drains of M3 and M4. I1 is referred to as the reference current, and I2 as the mirrored output current or bias current. The reference current I1 activates the gate of n-channel transistor M2 resulting in a voltage of VXN. The output current I2 having passed through transistor M2 flows through resistance R to generate voltage V which in turn provides gate voltage VG1 to the gate of n-channel transistor M1 to activate or “turn on” transistor M1. In this example, transistors M1 and M2 are n-channel transistors fabricated to have a positive threshold voltage. For example, the fabrication process includes a positive threshold voltage adjustment implant. I1 flows through transistor M1 creating the gate-source voltage VGS1, and current I2 flows through resistance R creating a voltage V=I2R. Because the two voltages are connected together, an equilibrium operating point Q is established at             I      2        ⁢                  ⁢    R    =            V      t1        +                                        2            ⁢                          I              1                                            K            N            ′                          ⁢                                  ⁢                              L            1                                W            1                                              wherein Vt1 is the threshold voltage for transistor M1, W1 is the width of its active area, L1 is the length of its active area, and K′N is the transconductance parameter for the n-channel transistor M1.        
This equation can be solved iteratively for I1=I2=IQ. Alternatively, VGS1 can be assumed to be approximately equal to Vt1 so that       I    Q    =            I      2        =                            V          t1                R            .      Since I1 or I2 does not change as a function of VDD, the sensitivity of IQ to changes in VDD is essentially zero.
Unfortunately, there are two possible equilibrium points in FIG. 1 at Q, one of which is undesired because it occurs at I1=I2=0. In FIG. 1, a problem comes about if M2 is turned off. This causes the voltage on the gates of M3 and M4 to go to VDD, resulting in turning them off so that the forward active currents I1 and I2=0. M2 does not receive enough leakage current from M3 to overcome its positive threshold voltage requirement so it is turned off. Without the forward active currents, the voltage across R and gate voltage of transistor M1 go to zero, turning them off and resulting in the undesirable equilibrium point at zero current.
In order to prevent the circuit from remaining at the undesired point, a start-up circuit such as the example 110 is necessary. The start-up circuit 110 comprises a resistance RB, a n-channel FET M7, and another n-channel FET M8. The resistance RB is connected to VDD on one side, and the other side of resistance RB is connected to the gate of n-channel FET M7 and to both a drain and a gate of n-channel FET M8. Transistor M7 has its drain connected to VDD, its gate connected to the other side of resistance RB as well as the drain of transistor M8, and its source connected to the drain of transistor M3, the drain of transistor M1 and the gate of transistor M2. The source of transistor M8 is connected to ground VSS.
The gate of transistor M7 is activated by the voltage across RB so that a forward active current flows from the source of M7 to the gate of transistor M2 causing M2 to “turn-on.” M2 would draw current I2 from the drain of M4 and generate a voltage across R, which in turn activates the gate of M1. The forward active current from transistor M7 provides a current to flow through M1. This current flowing through M1 causes the circuit to move to the desired equilibrium point. The gate voltage for M3 and M4 drops from VDD resulting in a forward active current in M3 that contributes to the current flow through transistor M1. Approaching the desired equilibrium point causes the source voltage of M7 to increase causing the current through M7 to decrease. At the desired equilibrium point, the current through M3 is essentially the current through M1.
FIG. 2 is another version of the reference circuit 100 of FIG. 1 which instead uses a base-emitter junction voltage VBE of a bipolar junction transistor (BJT) as the reference regulator 236 to reference the desired electrical characteristic of a voltage or a current.
In FIG. 2, circuit 200 comprises a base-emitter voltage-referenced circuit 220, and start-up circuit 210. (See, for example, Allen & Holberg, CMOS Analog Circuit Design, p. 240–251, Holt, Rinehart & Winston, New York 1987, which is hereby incorporated by reference).
The reference circuit 220 comprises a current mirror 234 including p-channel field effect transistors (FETs) M3 and M4, n-channel FETs M1 and M2, a reference regulator 236 implemented in this example as a bipolar junction transistor Q1 and a reference output regulator 238 implemented in this example as a resistance R.
The sources of p-channel transistors M3 and M4 are connected to positive voltage supply VDD. The drain of transistor M3 is connected to the gates of n-channel transistors M1 and M2 and also to the drain of n-channel transistor M1. The drain of p-channel transistor M4 is connected to the drain of n-channel transistor M2, and also to the gates of transistors M3 and M4. The gates of transistors M3 and M4 are connected together so that the output voltage VXP is supplied to the gates.
Similarly, the drain of n-channel transistor M1 is connected to the drain of M3 as illustrated (See VXN) and also to the gates of n-channel transistors M1 and M2. The source of n-channel transistor M1 is connected to the emitter of bipolar transistor Q1. The base and collector of Q1 are connected to a ground VSS. The source of transistor M2 is connected to one side of resistance R. Another side of resistance R is connected to ground VSS.
The p-channel transistors and the n-channel transistors form a feedback circuit which causes reference current I1 to be about equal to mirrored output current or bias current I2. The p-channel transistors M3 and M4 may also be described as a current mirror 234 supplying a reference current and its mirrored output to a current source comprising the configuration of the n-channel FETs M1 and M2, BJT Q1 and R. The current source provides a supply independent output or bias electrical characteristic.
In post-start-up operation, the p-channel transistors M3 and M4 are assumed to be matched devices forming a current mirror unit 234 producing equal currents, I1 and I2, to flow from the drains of M3 and M4. The reference current I1 activates the gates of n-channel transistors M1 and M2 so that the output current I2 flows through transistor M2 creating the gate-source voltage VGS2 and through resistance R creating a voltage V=I2R. In this example, transistors M1 and M2 are n-channel transistors fabricated to have a positive threshold voltage. I1 flows through transistor M1 creating the gate-source voltage VGS1 and through BJT Q1 creating the base-emitter junction voltage VBE. An equilibrium point is reached when the voltage I2R equals the base-emitter junction voltage VBE as illustrated by the equation:
I2R+VGS2=VBE1+VGS1       I    D    =            1      2        ⁢                  ⁢          K      p        ⁢                  ⁢          W      L        ⁢                  ⁢                  (                              V            GS                    -                      V            t                          )            2      In saturation       V    GS    =            V      t        +                                        2            ⁢                          I              D                                            K            p                          ⁢                                  ⁢                  L          W                    
Vt is the threshold voltage required to activate either of the FETs M1 or M2, and ID is the drain current of FET M1 or M2 in saturation.
Since I1=I2, then VGS1=VGS2, then             I      2        ⁢                  ⁢    R    =            V      BE1        =                            V          T                ⁢                                  ⁢        ln        ⁢                                  ⁢                  (                                    I              1                                      I              S                                )                ⁢                                  ⁢        or        ⁢                                  ⁢                  I          2                ⁢                                  ⁢        R            =                        V          BE1                =                              V            T                    ⁢                                          ⁢          ln          ⁢                                          ⁢                      (                                          I                2                                            I                S                                      )                              where       V    T    =      kT    q  is the thermal voltage and IS is the saturation current of Q1.
The current is set by the voltage on R matching the voltage drop VBE1 across the base-emitter junction of Q1.
As with the circuit in FIG. 1, there are two problems with this circuit: In addition to a desired equilibrium or stable operating point, an undesired second stable point exists at I2=I1=0. If VXN=0 V and VXP=5 V no current will flow. In order to prevent the circuit from operating at the undesired equilibrium point at I1=I2=0, a start-up circuit 210 is required. Start-up circuit 210 has the same configuration as the startup circuit example 110 except that the source of M7 is connected to both the gates of n-channel transistors M1 and M2. The current from M7 provides a current to both M1 and M2 to activate them and move operation of the reference circuit to the desired non-zero current equilibrium point Q. As in FIG. 1, as the source voltage of M7 increases, the current through M7 decreases so that M1 has essentially the same current I1 as M3, and M2 has essentially the same current I2 as M4 at the desired equilibrium point Q.
The second point is that the circuit requires VDD to be greater than the drop across VBE plus the threshold voltage Vt of the n-channel FETs M1 and M2 before VXP is a stable bias voltage.
It is highly desirable that a reference circuit avoid a second undesired stable operating point at which I1=I2=zero. In this way, a startup circuit may be eliminated, thereby reducing chip size in integrated circuits and decreasing the power required to power a startup circuit. Furthermore, it is also desirable that the threshold voltage Vt associated with the n-channel FETs not increase the voltage requirement of VDD in order to provide lower power implementations.